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Table of Contents
RVCore Project, Arch Lab, Tokyo Tech
The RVCore Project is a research and development project of the RISC-V soft processor highly optimized for FPGAs.
RVCoreP (RISC-V Core Pipelined version) is one of the RISC-V soft processor cores of the RVCore Project. It is an optimized RISC-V soft processor of five-stage pipelining.
RVCoreP supports the following FPGA boards!
- Nexys 4 DDR board with Xilinx Artix-7 FPGA
- Arty A7-35T board with Xilinx Artix-7 FPGA
What's new
- 2020/06/25 : Released Ver.0.5.3 and support the Arty A7-35T FPGA board
- 2020/05/18 : Add the page how to build the RISC-V cross compiler and RISC-V binary files
- 2020/05/17 : Change of web page structure and release of Ver.0.5.1
- 2020/05/03 : Added the setting method about New-line code
- 2020/03/04 : This page is released about Ver.0.4.6 !
About RVCoreP
The main specifications of RVCoreP are shown below:
- An optimized RISC-V soft processor
- Adopt RV32I of RISC-V as an instruction set architecture, which is the basic 32-bit integer instruction set
- Adopt five-stage pipelining
- Instruction fetch (If)
- Instruction decode (Id)
- Instruction execution (Ex)
- Memory access (Ma)
- Write back (Wb)
- Apply three effective optimization methods to improve the operating frequency
- Instruction fetch unit optimization including the pipelined branch prediction mechanism
- ALU optimization
- Data alignment and sign-extension optimization for data memory output
- Implemented in Verilog HDL
- Run RISC-V programs compiled with RV32I
- By Verilog HDL simulation using Verilator or Icarus Verilog
- On the FPGA boards including Xilinx Artix-7 FPGA
Download source file
The latest version of RVCoreP is Ver.0.5.3: rvcorep_ver053.zip
The other old versions are as follows:
- Ver.0.5.1: rvcorep_ver051.zip
- Ver.0.4.6: rvcorep_ver046.zip
This source code is released under the MIT License, see LICENSE.txt.
Change log
- Ver.0.5.3 : The version that supports Arty A7-35T FPGA board
- Ver.0.5.1 : The version supporting Verilator, Embench, pySerial, Vivado 2019.2
- Ver.0.4.6 : The version used in our submitted manuscript
Recommended environment
- Ubuntu 18.04 LTS
- Verilator for Verilog HDL simulation
- Icarus Verilog for Verilog HDL simulation
- Xilinx Vivado Design Suite 2019.2 for logic synthesis
- Nexys 4 DDR board or Arty A7-35T board with Xilinx Artix-7 FPGA for placement and routing
- Python 3.6.9
- pySerial for serial communication with FPGA board
–
> Install command #
Install verilator by the following command.
$ sudo apt install verilator
Install iverilog by the following command.
$ sudo apt install iverilog
Install pySerial by the following command.
$ sudo apt install python3-pip $ pip3 install pyserial
←-
Getting started guide
(1) Download the source code of the RVCoreP
$ wget http://www.arch.cs.titech.ac.jp/wk/rvcore/lib/exe/fetch.php?media=rvcorep_ver053.zip -O rvcorep_ver053.zip
(2) Extract the downloaded zip file
$ unzip rvcorep_ver053.zip $ cd rvcorep_ver053
–
> Verilog HDL simulation using Verilator #
You execute the following commands on the recommended environment.
(1) Compile source code written in Verilog HDL using Verilator
$ make verilator -DSERIAL_WCNT=2 -DNO_IP --public --top-module top --clk CLK --x-assign 0 --x-initial 0 --no-threads -O2 -Wno-WIDTH -Wno-UNSIGNED --exe sim.cpp --cc top.v main.v uart.v debug.v proc.v make -j -C obj_dir -f Vtop.mk Vtop cp obj_dir/Vtop simv
The executable file simv is generated after the compilation is performed.
(2) Execute the Verilog HDL simulation
By default, the test benchmark is executed.
The memory file of the test benchmark is test/test.mem.
–
> Execution result when running `test/test.mem` #
$ make run
./simv
Run test/test.mem
Initializing : ..........
--------------------------------------------------
---- nqueen ----
Nqueen :
N = 6
The number of solutions = 4
----------------
---- qsort ----
Sorted Seqence :
59321
A4C86
AC7D3
B210A
142044
1DEC15
1EC216
2536B2
278BCF
34A2AC
----------------
---- fib ----
Fibonacci Seqence :
1: 1
2: 1
3: 2
4: 3
5: 5
6: 8
7: D
8: 15
9: 22
A: 37
----------------
---- acker ----
acker(0,0) = 1
acker(0,1) = 2
acker(0,2) = 3
acker(1,0) = 2
acker(1,1) = 3
acker(1,2) = 4
acker(2,0) = 3
acker(2,1) = 5
acker(2,2) = 7
----------------
== elapsed clock cycles : 35030
== valid instructions executed : 28934
== IPC : 0.825
== branch prediction hit : 3615
== branch prediction miss : 1430
== branch prediction total : 5045
== branch prediction hit rate : 0.716
== the num of load-use stall : 1897
== estimated clock cycles : 35121
== r_cnt : 000088d6
== r_rout : 000000a0
- top.v:154: Verilog $finish
You will see the above output. The information such as IPC (Instructions Per Cycle) and branch prediction hit rate is output to the console after running simulation.
←-
(3) Execute the Dhrystone and Coremark benchmarks by the Verilog HDL simulation
You compile and execute with Dhrystone and Coremark benchmarks.
The memory files, the binary files, and the dump files are stored in the bench/ directory.
For Dhrystone, three configurations are prepared by the parameter NUMBER_OF_RUNS.
- benchd : NUMBER_OF_RUNS=500
- benchd2 : NUMBER_OF_RUNS=2000
- benchd3 : NUMBER_OF_RUNS=10000
For Coremark, three configurations are also prepared by the parameter ITERATIONS.
- benchc : ITERATIONS=1
- benchc2 : ITERATIONS=2
- benchc3 : ITERATIONS=10
These benchmarks can be run with the following commands.
$ make [configuration name] $ make run
(4) Execute the Embench benchmark by the Verilog HDL simulation
You compile and execute with 19 benchmarks in Embench.
The memory files, the binary files, and the dump files are stored in the embench/ directory.
These benchmarks can be run with the following commands.
$ make [benchmark name] $ make run
The execution results of dhrystone3, coremark3, and 19 benchmarks of Embench are summarized in the file result.txt.
←-
–
> Implementation and execution on a FPGA board #