RVCore Project, Arch Lab, Tokyo Tech
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RVCoreP (RISC-V Core Pipelined version) is one of the RISC-V soft processor cores of the RVCore Project.
It is an optimized RISC-V soft processor of five-stage pipelining.

## About RVCoreP

See the following page for details:

https://www.arch.cs.titech.ac.jp/wk/rvcore/doku.php

## Licence

This source code is released under the MIT License, see LICENSE.txt.

## Publication

This processor RVCoreP is explicated in a preprint paper of arXiv.

Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise:
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining, arXiv:2002.03568 [cs.AR] (2020-02-10).

## Contact

Kise Laboratory, Department of Computer Science, School of Computing, Tokyo Institute of Technology (Tokyo Tech)

E-mail: miyazaki (at) arch.cs.titech.ac.jp
