Kise Laboratory

Department of Computer Science, School of Computing, Institute of Science Tokyo

Selected Publications


Fiscal Year 2023 (April 2023 - March 2024) Updating

International Conference (Peer-reviewed)

  1. Kenji Kise: An open-source and GUI-capable RISC-V computer system on a low-end FPGA board, IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2023), pp.23-30 (Singapore, Presentation 2023-12-18) (December 2023).
  2. Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise: A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs, IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2023), pp.31-37 (Singapore, Presentation 2023-12-18) (December 2023).

Fiscal Year 2022 (April 2022 - March 2023) Updating

Journal

  1. Fumio Hamanaka, Takashi Odan, Kenji Kise, and Thiem Van Chu: An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration, IEEE Access, Vol.11, pp.5701-5713 (Janualy 2023).
  2. Takuto Kanamori, Takashi Odan, Kazuki Hirohata, and Kenji Kise: RVCar: An FPGA-based simple and open-source mini motor car system with a RISC-V soft processor, IEICE Transactions on Information and Systems, Vol.E105.D, No.12, pp.1999-2007 (December 2022).
  3. Md Ashraful Islam, and Kenji Kise: An efficient resource shared RISC-V multicore architecture, IEICE Transactions on Information and Systems, Vol.E105-D, No.9, pp.1506-1515 (September 2022).

Fiscal Year 2020 (April 2020 - March 2021) Updating

Journal

  1. Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, and Kenji Kise: RVCoreP: An optimized RISC-V soft processor of five-stage pipelining, IEICE Transactions on Information and Systems, Vol.E103-D, No.12, pp.2494-2503 (December 2020).
  2. Elsayed A. Elsayed, and Kenji Kise: High-Performance and Hardware-Efficient Odd-even Based Merge Sorter, IEICE Transactions on Information and Systems, Vol.E103-D, No.12, pp.2504-2517 (December 2020).

Preprint

  1. Takuto Kanamori, Hiromu Miyazaki, and Kenji Kise: RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions arXiv:2011.11246 [cs.AR] (2020-11-23).
  2. Md Ashraful Islam, Hiromu Miyazaki, and Kenji Kise: RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors, arXiv:2010.16171 [cs.AR] (2020-10-30).

Fiscal Year 2019 (April 2019 - March 2020) Updating

Journal

  1. Thiem Van Chu and Kenji Kise: LEF: An Effective Routing Algorithm for Two-Dimensional Meshes, IEICE Transactions on Information and Systems, Vol.E102-D, No.10, pp.1925-1941 (October 2019).

International Conference (Peer-reviewed)

  1. Thiem Van Chu, Kenji Kise and Kiyofumi Tanaka: Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs (accepted), 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020) (February 2020).
  2. Elsayed A. Elsayed and Kenji Kise: Towards an Efficient Hardware Architecture for Odd-even Based Merge Sorter, IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2019), pp.249-256 (Singapore, Presentation 2019-10-03) (October 2019).
  3. Katsunoshin Matsui, Md Ashraful Islam, and Kenji Kise: An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA, IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2019), pp.108-115 (Singapore, Presentation 2019-10-02) (October 2019).
  4. Hiromu Miyazaki, Junya Miura, and Kenji Kise: An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2019), pp.1-4 (Nagasaki Japan, Poster short speech 2019-06-06) (June 2019).

Preprint

  1. Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise: RVCoreP : An optimized RISC-V soft processor of five-stage pipelining, arXiv:2002.03568 [cs.AR] (2020-02-10).
  2. Junya Miura, Hiromu Miyazaki, Kenji Kise: A portable and Linux capable RISC-V computer system in Verilog HDL, arXiv:2002.03576 [cs.AR] (2020-02-10).

Fiscal Year 2018 (April 2018 - March 2019)

International Conference (Peer-reviewed)

  1. Makoto Saitoh and Kenji Kise: Very Massive Hardware Merge Sorter, The 2018 International Conference on Field-Programmable Technology (FPT'18), pp.89-96 (Okinawa Japan, Presentation 2018-12-12) (December 2018).
  2. Elsayed A. Elsayed and Kenji Kise: Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records, IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), pp.201-208 (Hanoi Vietnam, Presentation 2018-09-14) (September 2018).
  3. Yuuma Azuma, Hayato Sakagami and Kenji Kise: An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem, IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), pp.16-22 (Hanoi Vietnam, Presentation 2018-09-12) (September 2018).
  4. Thiem Van Chu and Kenji Kise: An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs, 28th International Symposium on Field-Programmable Logic and Applications (FPL 2018), pp.419-426 (Dublin Ireland, Presentation 2018-08-30) (August 2018).
  5. Kenji Kise: Swap-Based Merge Network for High Performance Sorting Accelerators, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2018), pp.1-6 (Toronto Canada, Presentation 2018-06-21) (June 2018).
  6. Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo and Kenji Kise: A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018), pp.197-204 (Boulder USA, Presentation 2018-05-01) (April 2018).

Fiscal Year 2017 (April 2017 - March 2018)

Journal

  1. Shimpei Sato, Ryohei Kobayashi and Kenji Kise: ArchHDL: A Novel Hardware RTL Modeling and High-speed Simulation Environment, IEICE Transactions on Information and Systems, Vol.E101-E, No.2, pp.344-353 (February 2018).
  2. Thiem Van Chu, Shimpei Sato and Kenji Kise: Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 10, Issue 4, Article No.27, pp.1-27 (December 2017).
  3. Ryohei Kobayashi, and Kenji Kise: A High Performance FPGA-based Sorting Accelerator with a Data Compression Mechanism, IEICE Transactions on Information and Systems, Vol.E100-D, No.5, pp.1003-1015 (May 2017).

International Conference (Peer-reviewed)

  1. Thiem Van Chu, Myeonggu Kang, Shi FA and Kenji Kise: Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip, IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2017), pp.83-90 (Seoul Korea, Presentation 2017-09-18) (September 2017).
  2. Susumu Mashimo, Thiem Van Chu, and Kenji Kise: High-Performance Hardware Merge Sorter(Best Paper Award), IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017), pp.1-8 (Napa USA, Presentation 2017-05-01) (April 2017).

Fiscal Year 2016 (April 2016 - March 2017)

International Conference (Peer-reviewed)

  1. Takuma Usui, Thiem Van Chu, and Kenji Kise: A Cost-effective and Scalable Merge Sorter Tree on FPGAs, International Symposium on Computing and Networking (CANDAR'16) (Hiroshima Japan, Presentation 2016-11-24) (November 2016).
  2. Eri Ogawa and Kenji Kise: An Effective Page Padding Method for RAM Buffer Algorithms to Enhance the SSD Endurance, International Symposium on Computing and Networking (CANDAR'16) (Hiroshima Japan, Presentation 2016-11-23) (November 2016).
  3. Masashi Imai, Thiem Van Chu, Kenji Kise, and Tomohiro Yoneda: The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs, IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) (Nara Japan, Presentation 2016-09-02) (August 2016).
  4. Susumu Mashimo, Thiem Van Chu, and Kenji Kise: Cost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2016), pp.7-12 (Hong Kong, Presentation 2016-07-25) (July 2016).
  5. Ryohei Kobayashi, Tomohiro Misono, and Kenji Kise: A High-speed Verilog HDL Simulation Method using a Lightweight Translator, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2016), pp.29-34 (Hong Kong, Presentation 2016-07-25) (July 2016).

Fiscal Year 2015 (April 2015 - March 2016)

Journal

  1. Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, and Kenji Kise: Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs, IEICE Transactions on Information and Systems, Vol.E98-D, No.12, pp.2150-2158 (December 2015).

International Conference (Peer-reviewed)

  1. Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, and Kenji Kise: Effective Parallel Simulation of ArchHDL under Manycore Environment, International Symposium on Computing and Networking -Across Practical Development and Theoretical Research- (CANDAR), pp.140-146 (Sapporo Japan, Presentation 2015-12-09) (December 2015).
  2. Yuki Matsuda, Ryosuke Sasakawa, and Kenji Kise: A Challenge for an Efficient AMI-Based Cache System on FPGA Soft Processors, International Symposium on Computing and Networking -Across Practical Development and Theoretical Research- (CANDAR), pp.133-139 (Sapporo Japan, Presentation 2015-12-09) (December 2015).
  3. Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, and Kenji Kise: Dependable Real-Time Task Execution Scheme for a Many-Core Platform, International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2015) (October 2015).
  4. Ryohei Kobayashi, and Kenji Kise: FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems, IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15), pp.49-56 (Turin Italy, Presentation 2015-09-23) (September 2015).
  5. Eri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, and Kenji Kise: Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research, IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15), pp.65-72 (Turin Italy, Presentation 2015-09-23) (September 2015).
  6. Thiem Van Chu, Shimpei Sato, and Kenji Kise: Ultra-Fast NoC Emulation on a Single FPGA, 25th International Symposium on Field-Programmable Logic and Applications (FPL 2015), pp.343-350 (London UK, Presentation 2015-09-03) (September 2015).
  7. Thiem Van Chu, Shimpei Sato, and Kenji Kise: Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a Single FPGA (short paper), The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2015), pp.60-63 (Vancouver Canada, Presentation 2015-05-04) (May 2015).
  8. Shimpei Sato, and Kenji Kise: ArchHDL: A Novel Hardware RTL Design Environment in C++, The 11th International Symposium on Applied Reconfigurable Computing (ARC 2015), pp.53-64, DOI: 10.1007/978-3-319-16214-0_5 (Bochum Germany,Presentation 2015-04-15) (April 2015).
  9. Takuma Usui, Ryohei Kobayashi, and Kenji Kise: A Challenge of Portable and High-speed FPGA Accelerator(short paper), The 11th International Symposium on Applied Reconfigurable Computing (ARC2015), pp.383-392, DOI: 10.1007/978-3-319-16214-0_34 (Bochum Germany) (April 2015).