Institute of Science Tokyo will be established
9/20 2024
Category: Announce
Institute of Science Tokyo will be established on October 1, 2024, following the merger between Tokyo Medical and Dental University and Tokyo Institute of Technology.
A new book on computer architecture
1/9 2024
Category: Announce
A new book on computer architecture will be published on February 24, 2024.
General co-chair of the ACM International Conference on Supercomputing
8/23 2023
Category: Announce
Prof. Kise will serve as the general co-chair of the ACM International Conference on Supercomputing (ICS 2024). Please visit the conference website.
Talk at the upcoming RISC-V Day Tokyo 2021 Spring
4/8 2021
Category: Announce
Prof. Kise will make a presentation at RISC-V DAY Tokyo 2021 Spring. The title is An easy-to-use Linux-compatible RISC-V personal computer on an FPGA starter board. Please visit this RISC-V event.
Our team won third place in the 2nd AI edge contest
4/30 2020
Category: Award
Our team of students Matsui, Nakono, Miura, and Miyazaki won third place in the 2nd AI edge contest where participants implemented image recognition systems in FPGAs and the processing performance in detecting target objects in images was the basis of the competition. The top three teams won awards in this contest with 377 participants (Trophy Photo).
The launch of Adaptive Computing Research Initiative, ACRi
4/1 2020
Category: Project
This research initiative is an organization that works on a variety of research themes on FPGA accelerations and FPGA infrastructures. Please visit our initiative website.
RVSoC (RISC-V System on Chip) Project
3/6 2020
Category: Project
This is a project to implement a portable and Linux capable RISC-V computer system named RVSoC (RISC-V System on Chip) on an FPGA. The source code of this system is written in Verilog HDL. Please visit our project website.
RVCore (RISC-V Core Pipelined version) Project
2/28 2020
Category: Project
This is a project to implement an optimized RISC-V soft processor in Verilog HDL. The number of lines of code for this system is just about 1,500. Please visit our project website.
Special Session on FPGA Technologies for Adaptive Computing
2/17 2020
Category: Announce
We will organize the Special Session on FPGA Technologies for Adaptive Computing (FTAC 2020) in conjunction with the IEEE MCSoC at Singapore University of Technology and Design (SUTD). Please visit our website.
The laboratory website was renewed.
11/25 2019
Category: Announce
This laboratory website has been renewed. For the time being, we will open only this English website.
Our paper has been accepted for FPGA 2020.
11/222019
Category: Publication
Our paper "Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs" has been accepted as a regular paper for FPGA 2020, which will be held in Seaside, California, USA. In this paper, we propose efficient methods and architectures to build a fast FPGA-based NoC emulator that supports trace-driven workloads with dependencies between packets taken into account. The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020) is the premier conference for presentation of advances in FPGA technology.
Our paper has been accepted for FCCM 2018.
3/142018
Category: Publication
Our paper "A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath" has been accepted as a regular paper for FCCM 2018, which will be held in Boulder, CO, USA. This paper proposes a high-performance and cost-effective hardware merge sorter (HMS) without any feedback datapaths in order to develop the fastest hardware sorting accelerator.
Received the FCCM 2017 Best Paper Award.
5/52016
Category: Award
We received the FCCM 2017 Best Paper Award. The IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware.