Computer Architecture (CSC.T363) Support Page, Dept. of Computer Science TOKYO TECH

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Final Exam

• 2024-12-03 (13:30-15:10) final exam in the computer room of the department of computer science

Materials for Computer Architecture Exercise

• Exercise_1 2024-10-08 (15:25-17:05): Exercise(1) Using an FPGA board, UART, Input/Output
• Exercise_2 2024-10-15 (15:25-17:05): Exercise(2) UART, Program Loader
• Exercise_3 2024-10-22 (15:25-17:05): Exercise(3) UART, Program Loader, Single-cycle Processor
• Exercise_4 2023-10-29 (15:25-17:05): Exercise(4) DRAM and cache
• Exercise_5 2024-11-12 (15:25-17:05): Exercise(5) Preparing the Computer Design Contest
• Exercise_6 2024-11-19 (15:25-17:05): Exercise(6) preparing the Computer Design Contest
• Exercise_7 2024-11-22 (13:30-15:10): Exercise(7) preparing the Computer Design Contest
• Exercise_8 2024-11-26 (13:30-17:05): Computer Design Contest, ContestSample.pptx

Lecture Slides and Materials

• Lecture_01 2024-10-04 (13:30-15:10): Guidance and Fundamentals of Computer Design, code201.v
• Lecture_02 2024-10-08 (13:30-15:10): Trends in Performance and Power, code202.v
• Lecture_03 2024-10-11 (13:30-15:10): Memory Technologies
• Lecture_04 2024-10-15 (13:30-15:10): Caches: Direct-Mapped
• Lecture_05 2024-10-18 (13:30-15:10): Caches: Set-Associative, main3_v2.v
• Lecture_06 2024-10-22 (13:30-15:10): Single-cycle Processor, rvcore1.pdf
• Lecture_07 2024-10-25 (13:30-15:10): Pipelined Processor
• Lecture_08 2024-10-29 (13:30-15:10): Branch Prediction
• Lecture_09 2024-11-01 (13:30-15:10): Branch Prediction (2)
• Lecture_10 2024-11-08 (13:30-15:10): Superscalar, Virtual Memory and Dependability (1)
• Lecture_11 2024-11-12 (13:30-15:10): Virtual Memory (2) and Dependability
• Lecture_12 2024-11-15 (13:30-15:10): Data-Level Parallelism in Vector and SIMD, Input/Output and Bus
• Lecture_13 2024-11-19 (13:30-15:10): Interconnection Network, Multiprocessors and Multicore
• Lecture_14 2024-11-22 (13:30-15:10): Exercise_7 (preparing the Computer Design Contest)

• RISC-V Reference Card
• XDC file for nexys4 DDR (nexys4 A7) with XC7A100T-1CSG324C FPGA
• bitstream file for nexys4 DDR (nexys4 A7) with XC7A100T-1CSG324C FPGA

Link

• CSC.T363 Computer Architecture Syllabus
• CSC.T341 Computer Logic Design Syllabus
• ACRi Room
• Computer Room, Department of Computer Science
• Venus RISC-V editor and simulator
• RV-PC: An open-source and GUI-capable RISC-V computer system
• Xilinx Vivado Design Suite
• Department of Computer Science, School of Computing, Institute of Ccience Tokyo
• GitHub Kise K.
• Kise Laboratory, Institute of Science Tokyo

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