Computer Architecture (CSC.T363) Support Page, Dept. of Computer Science, Science Tokyo

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Final Exam

• 2025-11-21 (13:30-15:10) final exam in the computer room of the department of computer science

Materials for Computer Architecture Exercise

• Exercise_1 2025-10-07 (15:25-17:05): Exercise(1) Using an FPGA board, UART, Input/Output, cp1-main.v, cp1-main.xdc, cp2-main.v, cp2-main.xdc, cp3-main.v, cp3-main.xdc
• Exercise_2 2025-10-14 (15:25-17:05): Exercise(2) CFU Proving Ground, UART, Program Loader, RECONF_CFU_PG.pdf, cfupg_test.bit, cp5-main.c
• Exercise_3 2025-10-21 (15:25-17:05): Exercise(3) UART, Program Loader, Single-cycle Processor
• Exercise_4 2023-10-28 (15:25-17:05): Exercise(4) DRAM and cache
• Exercise_5 2025-11-07 (15:25-17:05): Exercise(5) Preparing the Computer Design Contest
• Exercise_6 2025-11-11 (15:25-17:05): Exercise(6) preparing the Computer Design Contest
• Exercise_7 2025-11-25 (13:30-15:10): Computer Design Contest
• RISC-V cross compiler for Ubuntu (872MB file) rv32ima_for_ca.tgz

Lecture Slides and Materials

• Lecture_01 2025-10-03 (13:30-15:10): Guidance and Fundamentals of Computer Design
• Lecture_02 2025-10-07 (13:30-15:10): Trends in Performance and Power
• Lecture_03 2025-10-10 (13:30-15:10): Memory Technologies
• Lecture_04 2025-10-14 (13:30-15:10): Caches: Direct-Mapped
• Lecture_05 2025-10-17 (13:30-15:10): Caches: Set-Associative
• Lecture_06 2025-10-21 (13:30-15:10): Single-cycle Processor
• Lecture_07 2025-10-24 (13:30-15:10): Pipelined Processor
• Lecture_08 2025-10-28 (13:30-15:10): Branch Prediction
• Lecture_09 2025-10-31 (13:30-15:10): Branch Prediction (2)
• Lecture_10 2025-11-07 (13:30-15:10): Superscalar, Virtual Memory and Dependability (1)
• Lecture_11 2025-11-11 (13:30-15:10): Virtual Memory (2) and Dependability
• Lecture_12 2025-11-14 (13:30-15:10): Data-Level Parallelism in Vector and SIMD, Input/Output and Bus
• Lecture_13 2025-11-18 (13:30-15:10): Interconnection Network, Multiprocessors and Multicore
• Lecture_14 2025-11-18 (15:25-17:05): Exercise_7 (preparing the Computer Design Contest)

• RISC-V Reference Card
• XDC file for nexys4 DDR (nexys4 A7) with XC7A100T-1CSG324C FPGA
• bitstream file for nexys4 DDR (nexys4 A7) with XC7A100T-1CSG324C FPGA

Link

• CSC.T363 Computer Architecture Syllabus
• CSC.T341 Computer Logic Design Syllabus
• CFU Proving Ground
• ACRi Room
• Computer Room, Department of Computer Science
• Venus RISC-V editor and simulator
• RV-PC: An open-source and GUI-capable RISC-V computer system
• Xilinx Vivado Design Suite
• Department of Computer Science, School of Computing, Institute of Science Tokyo
• GitHub Kise K.
• Kise Laboratory, Institute of Science Tokyo

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