CSC.T433 Advanced Computer Architecture Support Page, Dept. of Computer Science TOKYO TECH

News

• This page is updated. (2020-12-03)
• This page is open. (2018-11-28)

Lecture Slides and Materials

• Lecture01 2020-12-03: Design and Analysis of Computer Systems
• Lecture02 2020-12-07: Instruction Set Architecture
• Lecture03 2020-12-10: Memory Hierarchy Design
• Lecture04 2020-12-14: Pipelining
• Lecture05 2020-12-17: Instruction Level Parallelism: Concepts and Challenges
• Lecture06 2020-12-21: canceled
• Lecture06 2020-12-24: Instruction Level Parallelism: Instruction Fetch and Branch Prediction
• Year-end holidays
• Lecture07 2021-01-07: Instruction Level Parallelism: Dynamic Scheduling
• Lecture08 2021-01-14: canceled
• Lecture08 2021-01-18: Instruction Level Parallelism: Exploiting ILP Using Multiple Issue and Speculation
• Lecture09 2021-01-21: Instruction Level Parallelism: Out-of-order Execution and Multithreading
• Lecture10 2021-01-25: Multi-Processor: Distributed Memory and Shared Memory Architecture
• Lecture11 2021-01-28: Thread Level Parallelism: Interconnection Network
• Lecture12 2021-02-01: Thread Level Parallelism: Coherence and Synchronization
• Lecture13 2021-02-04: Thread Level Parallelism: Memory Consistency Model
• Final Report

Materials for Advanced Computer Architecture

• MIPS/SPIM Reference Card
• counter.v
• proc01.v : single-cycle processor supporting ADD
• proc02.v : single-cycle processor supporting ADD and ADDI
• proc03.v : single-cycle processor supporting ADD, ADDI and LW
• proc04.v : single-cycle processor supporting ADD, ADDI, LW and SW
• proc06.v : Four stage pipelined processor supporting ADD, which has no data forwarding
• proc07.v : sample baseline for proc08.v
• proc08.v : Four stage pipelined processor supporting ADD and BNE, which has no data forwarding
• proc10.v : Four stage pipelined 2-way superscalar supporting ADD, which has no data forwarding

Links

• ACRi Room
• CSC.T363 Computer Architecture Support Page
• CSC.T341 Computer Logic Design Support Page
• Department of Computer Science, School of Computing, TOKYO TECH
• Kise Laboratory, TOKYO TECH
• Xilinx Vivado Design Suite

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