CSC.T433 Advanced Computer Architecture Support Page, Dept. of Computer Science TOKYO TECH

News

• This page is open. (2018-11-28)

Lecture Slides and Materials

• Lecture01 2019-12-02: Design and Analysis of Computer Systems
• Lecture02 2019-12-05: Instruction Set Architecture
• Lecture03 2019-12-09: Memory Hierarchy Design
• Lecture04 2019-12-12: Pipelining
• Lecture05 2019-12-16: canceled
• Lecture05 2019-12-19: Instruction Level Parallelism: Concepts and Challenges
• Lecture06 2019-12-23: Instruction Level Parallelism: Instruction Fetch and Branch Prediction
• Lecture07 2019-12-26: Instruction Level Parallelism: Instruction Fetch and Branch Prediction (2)
• Lecture08 2020-01-06: Instruction Level Parallelism: Dynamic Scheduling
• Lecture09 2020-01-09: Instruction Level Parallelism: Exploiting ILP Using Multiple Issue and Speculation
• Lecture10 2020-01-16: Instruction Level Parallelism: Out-of-order Execution and Multithreading
• Lecture11 2020-01-20: Multi-Processor: Distributed Memory and Shared Memory Architecture
• Lecture12 2020-01-23: Thread Level Parallelism: Interconnection Network
• Lecture13 2020-01-27: Thread Level Parallelism: Coherence and Synchronization
• Lecture14 2020-01-30: Thread Level Parallelism: Memory Consistency Model
• Final Report

Materials for Advanced Computer Architecture

• counter.v
• proc01.v : single-cycle processor supporting ADD
• proc02.v : single-cycle processor supporting ADD and ADDI
• proc03.v : single-cycle processor supporting ADD, ADDI and LW
• proc04.v : single-cycle processor supporting ADD, ADDI, LW and SW
• proc06.v : Four stage pipelined processor supporting ADD, which has no data forwarding
• proc07.v : A frame for proc08.v
• proc08.v : Four stage pipelined processor supporting ADD and BNE, which has no data forwarding
• proc10.v : Four stage pipelined 2-way superscalar supporting ADD, which has no data forwarding

Links

• CSC.T363 Computer Architecture Support Page
• CSC.T341 Computer Logic Design Support Page
• Department of Computer Science, School of Computing, TOKYO TECH
• Kise Laboratory, TOKYO TECH
• Xilinx Vivado Design Suite

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