CSC.T433 Advanced Computer Architecture

MIPS Reference Card
counter.v (Homework 1)
proc01.v: single-cycle processor supporting ADD
proc02.v: single-cycle processor supporting ADD and ADDI (Homework 2)
proc03.v: single-cycle processor supporting ADD, ADDI and LW
proc04.v: single-cycle processor supporting ADD, ADDI, LW and SW (Homework 3)
proc05.v: four stage pipelined processor supporting ADD, which uses wrong RD and does not adopt data forwarding, Block Diagram of proc05
proc06.v: four stage pipelined processor supporting ADD, which does not adopt data forwarding (Homework 4)
proc07.v: four stage pipelined processor supporting ADD and BNE without data forwarding, Block Diagram of proc07
proc08.v: four stage pipelined processor supporting ADD and BNE using Bimodal branch predictor, Block Diagram of proc08
proc10.v: four stage pipelined 2-way superscalar supporting ADD without data forwarding (Homework 5), Block Diagram of proc10
rename01.v: register renaming unit which renames one instruction per cycle
rename02.v: the baseline for register renaming unit which renames two instructions per cycle (Homework 6)