Kise Laboratory

Research on high-performance hardware sorter

You may have learned some sorting algorithms like bubble sort, quick sort, and merge sort. Sorting is one of the essential operations used in many areas. With the advent of new technologies such as social networks and IoT devices, there is a significant increase in the size of data to be processed. Therefore, improving the performance of sorting becomes critical.

The goal of this project is to establish effective architectures for high-performance hardware sorters targeting FPGAs.

Related publications

1. Elsayed A. Elsayed and Kenji Kise: Towards an Efficient Hardware Architecture for Odd-even Based Merge Sorter, IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2019) (October 2019).
2. Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo and Kenji Kise: A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018) (April 2018).
3. Susumu Mashimo, Thiem Van Chu, and Kenji Kise: High-Performance Hardware Merge Sorter, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017) (April 2017).

Research on RISC-V soft processor

The cost-effective soft processors for FPGAs like MicroBlaze from Xilinx are widely used. Here, a soft processor is a microprocessor that can be wholly implemented using logic synthesis, and can be implemented on a reconfigurable device like FPGA. Recently, RISC-V is becoming popular as a RISC based open instruction set architecture, and the demand for cost-effective soft processors based on RISC-V will become higher.

The goal of this project is to design and implement high-performance RISC-V soft processors.

Related publications

1. Katsunoshin Matsui, Md Ashraful Islam, and Kenji Kise: An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA, IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2019) (October 2019).
2. Hiromu Miyazaki, Junya Miura, and Kenji Kise: An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2019) (June 2019).

Research on Network-on-Chip system emulation

Modern high-performance many-core processors use Networks-on-Chip to move data around cores. As the number of cores increases, the overall processor performance becomes highly sensitive to NoC performance. Research and development of NoCs thus play a key role in designing future systems with hundreds to thousands of cores.

The goal of this project is to establish high-speed emulation schemes for modern Network-on-Chip using FPGAs.

Related publications

1. Thiem Van Chu, Kenji Kise and Kiyofumi Tanaka: Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020) (February 2020)
2. Thiem Van Chu and Kenji Kise: An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs, International Symposium on Field-Programmable Logic and Applications (FPL 2018) (August 2018).

Research on N-Queens acceleration using FPGAs

The N-Queens problem is a generalized problem with the 8-Queens puzzle, and the computational complexity of this problem is increased drastically when increasing N. To calculate the unsolved N-Queens problem in realistic time, implementing high-speed solvers and system is important.

The goal of this project is to design the system with high-speed solvers for N-Queens problem and to solve unsolved N-Queens problems.

Related publication

1. Yuuma Azuma, Hayato Sakagami and Kenji Kise: An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem, IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018) (September 2018).