Kise Labolatory
Kise Laboratory

Kise Laboratory
Department of Computer Science
Graduate School of Information Science and Engineering
Tokyo Institute of Technology
2-12-1|W8-79, Ookayama, Meguro-ku, Tokyo, 152-8552 Japan

members:

Associate Professor: Kenji KISE , E-mail: kise at cs.titech.ac.jp


Doctor Course: Ryosuke SASAKAWA , E-mail: sasakawa at arch.cs.titech.ac.jp


Doctor Course: Ryohei KOBAYASHI , E-mail: kobayashi at arch.cs.titech.ac.jp


Master Course: Haruka ASANO , E-mail: asano at arch.cs.titech.ac.jp


Master Course: Thiem Van Chu , E-mail: thiem at arch.cs.titech.ac.jp


Master Course: Tatsuya HASHIMOTO , E-mail: hashimoto at arch.cs.titech.ac.jp


Master Course: Haruka MORI , E-mail: morih at arch.cs.titech.ac.jp


Master Course: Kairi OKUMURA , E-mail: okumura at arch.cs.titech.ac.jp


Master Course: Yuki MATSUDA , E-mail: matsuda at arch.cs.titech.ac.jp


Master Course: Takuma USUI , E-mail: usui at arch.cs.titech.ac.jp


Master Course: Eri OGAWA , E-mail: ogawa at arch.cs.titech.ac.jp


Master Course: Susumu MASHIMO , E-mail: mashimo at arch.cs.titech.ac.jp


Master Course: Tomohiro MISONO , E-mail: misono at arch.cs.titech.ac.jp


Bachelor Course: Paniti Achararit , E-mail: paniti at arch.cs.titech.ac.jp


Bachelor Course: Shingo OHYA , E-mail: ohya at arch.cs.titech.ac.jp


Bachelor Course: Hiroto KAWAI , E-mail: kawai at arch.cs.titech.ac.jp


Bachelor Course: Masashi FUJINAMI , E-mail: fujinami at arch.cs.titech.ac.jp


research area: computer architecture

contact details:
Postal Address:

Kise Laboratory, Department of Computer Science
Graduate School of Information Science and Engineering,
Tokyo Institute of Technology 2-12-1|W8-79, Ookayama, Meguro-ku, Tokyo 152-8552 Japan

For all enquiries about the Labolatory, write to Kise at the address above or email:
kise at cs.titech.ac.jp
publications:
  • Ryohei Kobayashi, and Kenji Kise: FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems (accepted), IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15) (September 2015).
  • Eri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, and Kenji Kise: Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research (accepted), IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15) (September 2015).
  • Thiem Van Chu, Shimpei Sato, and Kenji Kise: Ultra-Fast NoC Emulation on a Single FPGA (accepted), 25th International Symposium on Field-Programmable Logic and Applications (FPL 2015), (London UK) (September 2015).
  • Thiem Van Chu, Shimpei Sato, and Kenji Kise: Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a Single FPGA (short paper), The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2015), pp.60-63 (Vancouver Canada, Presentation 2015-05-04) (May 2015).
  • Shimpei Sato, and Kenji Kise: ArchHDL: A Novel Hardware RTL Design Environment in C++, The 11th International Symposium on Applied Reconfigurable Computing (ARC 2015), pp.53-64, DOI: 10.1007/978-3-319-16214-0_5 (Bochum Germany,Presentation 2015-04-15) (April 2015).
  • Takuma Usui, Ryohei Kobayashi, and Kenji Kise: A Challenge of Portable and High-speed FPGA Accelerator(short paper), The 11th International Symposium on Applied Reconfigurable Computing (ARC2015), pp.383-392, DOI: 10.1007/978-3-319-16214-0_34 (Bochum Germany) (April 2015).
  • Shinya Takamaeda-Yamazaki and Kenji Kise: A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2014) (December 2014).
  • Thiem Van Chu, Shimpei Sato, and Kenji Kise: KNoCEmu: High Speed FPGA-Emulator for a Kilo-Node Scale NoC, IEEE 8th International Symposium on Embedded Multicore SoCs (MCSoC-14), pp.215-222 (September 2014).
  • Haruka Mori, and Kenji Kise: Design and Performance Evaluation of a Manycore Processor for Large FPGA, IEEE 8th International Symposium on Embedded Multicore SoCs (MCSoC-14), pp.207-214 (September 2014).
  • Takakazu Ikeda, and Kenji Kise: Application Aware DRAM Bank Partitioning in CMP, The 19th IEEE International Conference on Parallel and Distributed Systems (ICPADS), pp.349-356 (Seoul Korea, Presentation 2013-12-18) (December 2013).
  • Shinya Takamaeda, Kenji Kise, and James C. Hoe: PyCoRAM: Yet Another Implementation of CoRAM Memory Architecture for Modern FPGA-based Computing, The Third Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013), pp.1-6 (Davis California USA, Presentation 2013-12-07) December 2013.
  • Ryosuke Sasakawa, and Kenji Kise: LEF: Long Edge First Routing for Two-Dimensional Mesh Network on Chip, Fifth International Workshop on Network on Chip Architectures (NoCArc), pp.5-10 (Davis California USA, Presentation 2013-12-08) (December 2013).
  • Shimpei Sato, and Kenji Kise: ArchHDL: A New Hardware Description Language for High-Speed Architectural Evaluation, IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-13), pp.107-112 (Tokyo Japan, Presentation 2013-09-28) (September 2013).
  • Tomoyuki Nagatsuk, and Kenji Kise: Design and Implementation of an Efficient and Realistic Cooperative Core Architecture, IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-13), pp.13-18 (Tokyo Japan, Presentation 2013-09-26) (September 2013).
  • Yuichiro Tanaka, Shimpei Sato, and Kenji Kise: The Ultrasmall Soft Processor, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2013), pp.63-68 (June 2013).
  • Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, and Kenji Kise: Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations, Third International Conference on Networking and Computing, pp.343-349 (December 2012).
  • Takakazu Ikeda, Shinya Takamaeda-Yamazaki, Naoki Fujieda, Shimpei Sato, and Kenji Kise: Read Density Aware Fair Memory Scheduling (Performance Track Award), 3rd JILP Workshop on Computer Architecture Competitions (JWAC-3): Memory Scheduling Championship (MSC) in conjunction with ISCA-39th, pp.1-6 (June 2012).
  • Tomoyuki Nagatsuka, Yoshito Sakaguchi, and Kenji Kise: CoreSymphony Architecture, ACM International Conference on Computing Frontiers, pp.249-252, DOI: 10.1145/2212908.2212945 (May 2012).
  • Shinya Takamaeda, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, and Kenji Kise: ScalableCore System: A Scalable Many-core Simulator by Employing Over 100 FPGA, The 8th International Symposium on Applied Reconfigurable Computing (ARC 2011), Lecture Notes in Computer Science, Vol.7199/2012, pp.138-150, DOI: 10.1007/978-3-642-28365-9_12 (March 2012).
  • Naoki Fujieda and Kenji Kise: A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors, Third Workshop on Ultra Performance and Dependable Acceleration Systems held in conjunction with ICNC'11, pp.160-165 (December 2011).
  • Mochamad Asri, Naoki Fujieda, and Kenji Kise: Rethinking Processor Instruction Fetch:Inefficiencies-Cracking Mechanism, International SoC Design Conference (ISOCC2011) (November 2011).
  • Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, and Kenji Kise: CoreSymphony: An Efficient Reconfigurable Multi-core Architecture, COMPUTER ARCHITECTURE NEWS, Vol.39, No.4, pp.32-37 (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies HEART2011, pp. 29-34, June 2011), DOI: 10.1145/2082156.2082165 (September 2011).
  • Shinya Takamaeda, Ryosuke Sasakawa, Yoshito Sakaguchi, and Kenji Kise: An FPGA-based Scalable Simulation Accelerator for Tile Architectures, COMPUTER ARCHITECTURE NEWS, Vol.39, No.4, pp.38-43 (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies HEART2011, pp. 35-40, June 2011), DOI: 10.1145/2082156.2082166 (Septermber 2011).
  • Kenji Kise and Masahiro Sano: Software Distributed Shared Memory System for Many-core Architectures, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA-2011), pp.1-3 (April 2011).
  • Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise: SmartCore System for Dependable Many-core Processor with Multifunction Routers, International Conference on Networking and Computing (ICNC'10), pp.133-139 (November 2010).
  • Takefum Miyoshi, Kenji Kise, Hidetsugu Irie, and Tsutomu Yoshinaga: CODIE: Continuation-based Overlapping Data-transfers with Instruction Execution, International Conference on Networking and Computing (ICNC'10), pp.71-77 (November 2010).
  • Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise: Pattern-based Systematic Task Mapping for Many-core Processors, Workshop on Ultra Performance and Dependable Acceleration Systems held in conjunction with ICNC'10, pp.173-178 (November 2010).
  • Naoki Fujieda, Takefumi Miyoshi, and Kenji Kise: SimMips: A MIPS System Simulator, Workshop on Computer Architecture Education (WCAE) held in conjunction with MICRO-42, pp. 32-39 (December 2009).
  • Yuhta Wakasugi, Naoki Fujieda, Shinya Takamaeda, and Kenji Kise: MipsCoreDuo: A Multifunction Dual-core Processor, International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 587-590 (December 2009).
  • Koh Uehara, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise: A Study of an Infrastructure for Research and Development of Many-Core Processors, International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT), pp. 414-419 (December 2009).
  • Yusuke Mori and Kenji Kise: The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors, International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT), pp. 445-450 (December 2009).
  • Shinya Takamaeda, Shimpei Watanabe, Takefumi Miyoshi, and Kenji Kise: ScalableCore : The Concept of Practical and Low-Cost Prototyping System for Many-Core Processor Research and Education, The 4th Workshop on Architectural Research Prototyping (WARP 2009) held in conjunction with the ISCA-2009, pp. 1-2 (June 2009).
  • Takashi Nakada, Yasuhiko Nakashima, Hajime Shimada, Kenji Kise, and Toshiaki Kitamura: OROCHI: A Multiple Instruction Set SMT Processor, International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC), pp. 1-8 (November 2008).
  • Shimpei Sato, Naoki Fujieda, Akira Moriya, and Kenji Kise: Processor Simulator SimCell to Accelerate Research on Many-core Processor Architectures, Workshop on Cell Systems and Applications (WCSA 2008) held in conjunction with the ISCA-2008, pp. 119-127 (June 2008).
  • Hajime Shimada, Takashi Shimada, Takekazu Tabata, Toshiaki Kitamura, Tomoya Kojima, Yasuhiko Nakashima and Kenji Kise: Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor, International Workshop on Innovative Architecture for Future Generation Processors and Systems (IWIA-2007), pp. 110-117 IEEE Computer Society Press (2007).