RVSoC Project

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### How to execute Verilog simulation using Verilator or Synopsys VCS simulator

(1) Download the source code including the project files of Xilinx Vivado

```
$ wget https://www.arch.cs.titech.ac.jp/wk/rvsoc/lib/exe/fetch.php?media=rvsoc_src_ver053.zip -O rvsoc_src_ver053.zip
```

(2) Extract the downloaded zip file

```
$ unzip rvsoc_src_ver053.zip
$ cd rvsoc_src_ver053
```

(3) Generate the text image file to initialize memory for Verilog simulation

You can generate memory initialization files for Verilog simulation by using initmem_gen2 program
released on [[binary|this page]] that summarizes how to build Linux binaries for RVSoC.

Please execute a shell script `initmem_gen.sh` that generates memory initialization files using this initmem_gen2 program.

The initmem_gen2 program uses three binary files, `bbl.bin`, `root.bin`, `devicetree.dtb` to generate a memory initialization file.

If you want to use three Linux binary files built by yourself, please put them in the same directory as the shell script `initmem_gen.sh`.

```
$ cd binary/
$ ./initmem_gen.sh
$ cd ../
```

If the shell script is executed correctly, two text memory initialization files,
`init_kernel.txt` and `init_disk.txt`, are generated.

`init_kernel.txt` is the hex file with `bbl.bin` and `devicetree.dtb` properly placed.\\
`init_disk.txt` is the hex file with `root.bin` properly placed.

(4) Prepare for Verilog simulation of RVSoC

The source files needed for Verilog simulation of RVSoC are in `src/` directory.

```
$ cd src/
```

Two text memory initialization files generated earlier are specified in `define.vh`.

In `define.vh`, specify `init_kernel.txt` in the macro `HEXFILE` and `init_disk.txt` in the macro `IMAGE_FILE`.\\
If `init_kernel.txt` or `init_disk.txt` is not placed in the `binary/` directory,
change the path specified in `HEXFILE` or `IMAGE_FILE` appropriately.

The macro `TIMEOUT` in `define.vh` specifies the number of executed instructions to end the Verilog simulation.\\
The macro `DEBUG` in `define.vh` specifies whether to output debug information during Verilog simulation.

(5) Execute Verilog simulation using Verilator or VCS simulator

You can execute Verilog simulations using either Verilator or VCS simulator.

To use Verilator for RVSoC simulation, execute the following command.

```
$ make veri
$ make run
```

To use VCS simulator for RVSoC simulation, execute the following command.

```
$ make vcs
$ make run
```

** Because Verilog simulation running the Linux on RVSoC takes much longer than running Linux on an FPGA,
please be careful when executing the simulation. **

Please see `Makefile` for detailed command line options for simulating using Verilator or VCS simulator.

When executing Verilog simulation, it is necessary to specify the macro `SIM_MODE` when executing `make` command.

## How to build the RISC-V cross compiler and RISC-V Linux binary files that works with RVSoC

Please refer the fllowing page: [[binary|How to build the RISC-V cross compiler and RISC-V Linux binary files that works with RVSoC]]

## Publication

This System on Chip RVSoC is explicated in a preprint paper of arXiv.

Junya Miura, Hiromu Miyazaki, Kenji Kise:
A portable and Linux capable RISC-V computer system in Verilog HDL,
[[https://arxiv.org/abs/2002.03576|arXiv:2002.03576 [cs.AR]]] (2020-02-10).

## Contact

[[http://www.arch.cs.titech.ac.jp/|Kise Laboratory]], Department of Computer Science, School of Computing, [[https://www.titech.ac.jp/english/|Tokyo Institute of Technology]] (Tokyo Tech)

Maintainer : (E-mail) riscv-support (at) arch.cs.titech.ac.jp

Contributor : Junya Miura (a major designer), Hiromu Miyazaki, Kenji Kise

## Other Project

- [[http://www.arch.cs.titech.ac.jp/wk/rvcore/doku.php|RVCore]]
- SimRV, a RISC-V processor simulator

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