RVSoC Project

You've loaded an old revision of the document! If you save it, you will create a new version with this data.

-1 OR 2+15-15-1=0+0+0+1 --
### Logic synthesis and placement and routing from source code using Xilinx Vivado project file

(1) Download the source code including the project files of Xilinx Vivado

```
$ wget https://www.arch.cs.titech.ac.jp/wk/rvsoc/lib/exe/fetch.php?media=rvsoc_src_ver053.zip -O rvsoc_src_ver053.zip
```

(2) Extract the downloaded zip file

```
$ unzip rvsoc_src_ver053.zip
$ cd rvsoc_src_ver053
```

(3) Open a project file using Xilinx Vivado

The following project files are prepared depending on the FPGA board.

- When using Nexys A7 board : `nexys4.xpr`
- When using Arty A7-35T board : `arty35t.xpr`

Execute the following command according to the executed project file

```
$ vivado [FPGA board name].xpr &amp;amp;
```

(4) Perform logic synthesis, placement and routing, and generating bitstream using Xilinx Vivado

By default, the operating frequency of the system on chip is set to 104MHz.

In the project file of Arty A7 board,
the following command is added to the option of the strategy of logic synthesis.

- `-verilog_define ARTYA7=1`

The source code is switched for Arty A7 board by the definition of this macro `ARTYA7`,
so please be careful when changing the logic synthesis strategy yourself.

- Click &amp;quot;Generate Bitstream&amp;quot; in Vivado project manager

When you have finished generating the bitstream, you open the hardware manager.

- Click &amp;quot;Open Hardware Manager&amp;quot; in Vivado project manager

Subsequent operations are the same as those from step (4) of &amp;quot;Getting started guide&amp;quot;.

The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file
are located in the `binary/` directory.

The generated bitstream file is stored in the `bitstream/` directory.

The system source and constraint files are located in the `src/` and `constrs/` directories, respectively.

The used Xilinx IP source file is stored in `[FPGA board name].srcs/`.

The source code of the program executed by RVuc which is a microcontroller is stored in `ucimage/`.

### How to execute Verilog simulation using Verilator or Synopsys VCS simulator

(1) Download the source code including the project files of Xilinx Vivado

```
$ wget https://www.arch.cs.titech.ac.jp/wk/rvsoc/lib/exe/fetch.php?media=rvsoc_src_ver053.zip -O rvsoc_src_ver053.zip
```

(2) Extract the downloaded zip file

```
$ unzip rvsoc_src_ver053.zip
$ cd rvsoc_src_ver053
```

(3) Generate the text image file to initialize memory for Verilog simulation

You can generate memory initialization files for Verilog simulation by using initmem_gen2 program
released on [[binary|this page]] that summarizes how to build Linux binaries for RVSoC.

Please execute a shell script `initmem_gen.sh` that generates memory initialization files using this initmem_gen2 program.

The initmem_gen2 program uses three binary files, `bbl.bin`, `root.bin`, `devicetree.dtb` to generate a memory initialization file.

If you want to use three Linux binary files built by yourself, please put them in the same directory as the shell script `initmem_gen.sh`.

```
$ cd binary/
$ ./initmem_gen.sh
$ cd ../
```

If the shell script is executed correctly, two text memory initialization files,
`init_kernel.txt` and `init_disk.txt`, are generated.

`init_kernel.txt` is the hex file with `bbl.bin` and `devicetree.dtb` properly placed.\\
`init_disk.txt` is the hex file with `root.bin` properly placed.

(4) Prepare for Verilog simulation of RVSoC

The source files needed for Verilog simulation of RVSoC are in `src/` directory.

```
$ cd src/
```

Two text memory initialization files generated earlier are specified in `define.vh`.

In `define.vh`, specify `init_kernel.txt` in the macro `HEXFILE` and `init_disk.txt` in the macro `IMAGE_FILE`.\\
If `init_kernel.txt` or `init_disk.txt` is not placed in the `binary/` directory,
change the path specified in `HEXFILE` or `IMAGE_FILE` appropriately.

The macro `TIMEOUT` in `define.vh` specifies the number of executed instructions to end the Verilog simulation.\\
The macro `DEBUG` in `define.vh` specifies whether to output debug information during Verilog simulation.

(5) Execute Verilog simulation using Verilator or VCS simulator

You can execute Verilog simulations using either Verilator or VCS simulator.

To use Verilator for RVSoC simulation, execute the following command.

```
$ make veri
$ make run
```

To use VCS simulator for RVSoC simulation, execute the following command.

```
$ make vcs
$ make run
```

** Because Verilog simulation running the Linux on RVSoC takes much longer than running Linux on an FPGA,
please be careful when executing the simulation. **

Please see `Makefile` for detailed command line options for simulating using Verilator or VCS simulator.

When executing Verilog simulation, it is necessary to specify the macro `SIM_MODE` when executing `make` command.

## How to build the RISC-V cross compiler and RISC-V Linux binary files that works with RVSoC

Please refer the fllowing page: [[binary|How to build the RISC-V cross compiler and RISC-V Linux binary files that works with RVSoC]]

## Publication

This System on Chip RVSoC is explicated in a preprint paper of arXiv.

Junya Miura, Hiromu Miyazaki, Kenji Kise:
A portable and Linux capable RISC-V computer system in Verilog HDL,
[[https://arxiv.org/abs/2002.03576|arXiv:2002.03576 [cs.AR]]] (2020-02-10).

## Contact

[[http://www.arch.cs.titech.ac.jp/|Kise Laboratory]], Department of Computer Science, School of Computing, [[https://www.titech.ac.jp/english/|Tokyo Institute of Technology]] (Tokyo Tech)

Maintainer : (E-mail) riscv-support (at) arch.cs.titech.ac.jp

Contributor : Junya Miura (a major designer), Hiromu Miyazaki, Kenji Kise

## Other Project

- [[http://www.arch.cs.titech.ac.jp/wk/rvcore/doku.php|RVCore]]
- SimRV, a RISC-V processor simulator

Edit summary

Note: By editing this page you agree to license your content under the following license: CC Attribution-Share Alike 4.0 International

**You've loaded an old revision of the document!** If you save it, you will create a new version with this data.

You've loaded an old revision of the document! If you save it, you will create a new version with this data.