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### Logic synthesis and placement and routing from source code using Xilinx Vivado project file

(1) Download the source code including the project files of Xilinx Vivado

```
$ wget https://www.arch.cs.titech.ac.jp/wk/rvsoc/lib/exe/fetch.php?media=rvsoc_src_ver053.zip -O rvsoc_src_ver053.zip
```

(2) Extract the downloaded zip file

```
$ unzip rvsoc_src_ver053.zip
$ cd rvsoc_src_ver053
```

(3) Open a project file using Xilinx Vivado

The following project files are prepared depending on the FPGA board.

- When using Nexys A7 board : `nexys4.xpr`
- When using Arty A7-35T board : `arty35t.xpr`

Execute the following command according to the executed project file

```
$ vivado [FPGA board name].xpr &amp;
```

(4) Perform logic synthesis, placement and routing, and generating bitstream using Xilinx Vivado

By default, the operating frequency of the system on chip is set to 104MHz.

In the project file of Arty A7 board,
the following command is added to the option of the strategy of logic synthesis.

- `-verilog_define ARTYA7=1`

The source code is switched for Arty A7 board by the definition of this macro `ARTYA7`,
so please be careful when changing the logic synthesis strategy yourself.

- Click "Generate Bitstream" in Vivado project manager

When you have finished generating the bitstream, you open the hardware manager.

- Click "Open Hardware Manager" in Vivado project manager

Subsequent operations are the same as those from step (4) of "Getting started guide".

The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file
are located in the `binary/` directory.

The generated bitstream file is stored in the `bitstream/` directory.

The system source and constraint files are located in the `src/` and `constrs/` directories, respectively.

The used Xilinx IP source file is stored in `[FPGA board name].srcs/`.

The source code of the program executed by RVuc which is a microcontroller is stored in `ucimage/`.

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