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| start-1_waitfor_delay_0:0:15 [2024/12/09 02:41] – [Logic synthesis and placement and routing from source code using Xilinx Vivado project file] 94.103.125.62 | start-1_waitfor_delay_0:0:15 [2024/12/09 06:19] (current) – [How to build the RISC-V cross compiler and RISC-V Linux binary files that works with RVSoC] 94.103.125.62 | ||
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| Line 249: | Line 249: | ||
| ``` | ``` | ||
| - | $ vivado [FPGA board name].xpr & | + | $ vivado [FPGA board name].xpr & |
| ``` | ``` | ||
| Line 264: | Line 264: | ||
| so please be careful when changing the logic synthesis strategy yourself. | so please be careful when changing the logic synthesis strategy yourself. | ||
| - | - Click "Generate Bitstream& | + | - Click "Generate Bitstream" |
| When you have finished generating the bitstream, you open the hardware manager. | When you have finished generating the bitstream, you open the hardware manager. | ||
| - | - Click "Open Hardware Manager& | + | - Click "Open Hardware Manager" |
| - | Subsequent operations are the same as those from step (4) of "Getting started guide". | + | Subsequent operations are the same as those from step (4) of "Getting started guide". |
| The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file | The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file | ||
start-1_waitfor_delay_0/0/15.1733679694.txt.gz · Last modified: 2024/12/09 02:41 by 94.103.125.62