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| start [2026/02/15 11:14] – [How to execute Verilog simulation using Verilator or Synopsys VCS simulator] 157.230.240.151 | start [2026/02/15 11:56] (current) – [Logic synthesis and placement and routing from source code using Xilinx Vivado project file] 157.230.240.151 | ||
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| ** (An EXT4-fs error may occur when the first command is executed after login, | ** (An EXT4-fs error may occur when the first command is executed after login, | ||
| but there is no problem because the subsequent commands are executed correctly.) ** | but there is no problem because the subsequent commands are executed correctly.) ** | ||
| - | |||
| Line 249: | Line 248: | ||
| ``` | ``` | ||
| - | $ vivado [FPGA board name].xpr & | + | $ vivado [FPGA board name].xpr & |
| ``` | ``` | ||
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