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if_now_sysdate_sleep_15_0 [2025/10/11 16:22] – [Getting started guide] 104.233.166.1if_now_sysdate_sleep_15_0 [2026/02/15 11:25] (current) – [How to build the RISC-V cross compiler and RISC-V Linux binary files that works with RVSoC] 157.230.240.151
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 - [[https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual|Arty A7-35T board]] with Xilinx Artix-7 FPGA - [[https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual|Arty A7-35T board]] with Xilinx Artix-7 FPGA
  
-{{:sit3-shine.7.gif?nolink&50|}}+{{:sit3-shine.7.gif?nolink&50|}}
  
  
-{{:welcom2.png?nolink&1200|}}+{{:welcom2.png?nolink&1200|}}
  
  
  
-## What's new+## What's new
  
 - 2020/08/24 : Released Ver.0.5.3 that can execute Verilog simulation using Verilator - 2020/08/24 : Released Ver.0.5.3 that can execute Verilog simulation using Verilator
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 ``` ```
-$ vivado &+$ vivado &
 ``` ```
  
-- Click "Open Hardware Manager" in "Task" at the top page+- Click "Open Hardware Manager" in "Task" at the top page
  
 (4) Write the bitstream file to a FPGA board (4) Write the bitstream file to a FPGA board
  
-- Click "Open target" and "Auto Connect" to recognize a FPGA board+- Click "Open target" and "Auto Connect" to recognize a FPGA board
  
-- Click "Program device" and a specify Bitstream file+- Click "Program device" and a specify Bitstream file
   - When using Nexys A7 board : `nexys4.bit`   - When using Nexys A7 board : `nexys4.bit`
   - When using Arty A7-35T board : `arty35t.bit`   - When using Arty A7-35T board : `arty35t.bit`
  
-- Click "Program" to write bitstream to a FPGA board+- Click "Program" to write bitstream to a FPGA board
  
 When the bitstream data is correctly written to the Nexys A7 board, When the bitstream data is correctly written to the Nexys A7 board,
-the DONE LED lights up and "ArchProc" is displayed on the 8-digit 7-segment LEDs.+the DONE LED lights up and "ArchProc" is displayed on the 8-digit 7-segment LEDs.
 Also, the lower right LED will blink at regular intervals,  Also, the lower right LED will blink at regular intervals, 
  
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 ``` ```
-$ gtkterm &+$ gtkterm &
 ``` ```
  
-- Click "Configuration"->"Port"+- Click "Configuration"->"Port"
 - Change the Port of Serial port to the appropriate USB Serial Port like `/dev/ttyUSB1` - Change the Port of Serial port to the appropriate USB Serial Port like `/dev/ttyUSB1`
 - Change the Baud Rate of Serial port to “8000000” and click “OK” - Change the Baud Rate of Serial port to “8000000” and click “OK”
-- Click "Configuration"->"CR LF auto" for New-line code+- Click "Configuration"->"CR LF auto" for New-line code
  
 Second, check the setting of the port used for serial communication in the pySerial program `serial_sendfile.py`. Second, check the setting of the port used for serial communication in the pySerial program `serial_sendfile.py`.
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 ``` ```
-$ python3 serial_sendfile.py 8 "initmem.bin"+$ python3 serial_sendfile.py 8 "initmem.bin"
 ``` ```
  
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 The program is automatically terminated when the transmission is completed. The program is automatically terminated when the transmission is completed.
  
-Confirm that "finished!" is displayed on the console of the terminal.+Confirm that "finished!" is displayed on the console of the terminal.
  
 Linux starts up and a Linux startup message is displayed on the GTKTerm console. Linux starts up and a Linux startup message is displayed on the GTKTerm console.
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 ``` ```
-$ vivado [FPGA board name].xpr &+$ vivado [FPGA board name].xpr &
 ``` ```
  
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 so please be careful when changing the logic synthesis strategy yourself. so please be careful when changing the logic synthesis strategy yourself.
  
-- Click "Generate Bitstream" in Vivado project manager+- Click "Generate Bitstream" in Vivado project manager
  
 When you have finished generating the bitstream, you open the hardware manager. When you have finished generating the bitstream, you open the hardware manager.
  
-- Click "Open Hardware Manager" in Vivado project manager+- Click "Open Hardware Manager" in Vivado project manager
  
-Subsequent operations are the same as those from step (4) of "Getting started guide".+Subsequent operations are the same as those from step (4) of "Getting started guide".
  
 The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file
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 Copyright (c) 2020 Kise Laboratory, Tokyo Institute of Technology Copyright (c) 2020 Kise Laboratory, Tokyo Institute of Technology
 +1
if_now_sysdate_sleep_15_0.1760167340.txt.gz · Last modified: 2025/10/11 16:22 by 104.233.166.1