if_now_sysdate_sleep_15_0
Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| if_now_sysdate_sleep_15_0 [2025/10/11 16:18] – [Logic synthesis and placement and routing from source code using Xilinx Vivado project file] 104.233.166.1 | if_now_sysdate_sleep_15_0 [2025/10/11 16:22] (current) – [Getting started guide] 104.233.166.1 | ||
|---|---|---|---|
| Line 249: | Line 249: | ||
| ``` | ``` | ||
| - | $ vivado [FPGA board name].xpr & | + | $ vivado [FPGA board name].xpr & |
| ``` | ``` | ||
| Line 264: | Line 264: | ||
| so please be careful when changing the logic synthesis strategy yourself. | so please be careful when changing the logic synthesis strategy yourself. | ||
| - | - Click "Generate Bitstream& | + | - Click "Generate Bitstream" |
| When you have finished generating the bitstream, you open the hardware manager. | When you have finished generating the bitstream, you open the hardware manager. | ||
| - | - Click "Open Hardware Manager& | + | - Click "Open Hardware Manager" |
| - | Subsequent operations are the same as those from step (4) of "Getting started guide". | + | Subsequent operations are the same as those from step (4) of "Getting started guide". |
| The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file | The Linux binary file `initmem.bin` sent to the FPGA and the program `serial_sendfile.py` that sends the binary file | ||
if_now_sysdate_sleep_15_0.1760167138.txt.gz · Last modified: 2025/10/11 16:18 by 104.233.166.1