RVCore Project, Arch Lab, Tokyo Tech

The RVCore Project is a research and development project of the RISC-V soft processor highly optimized for FPGAs.

RVCoreP (RISC-V Core Pipelined version) is one of the RISC-V soft processor cores of the RVCore Project. It is an optimized RISC-V soft processor of five-stage pipelining.

RVCoreP supports the following FPGA boards!

• Nexys 4 DDR board with Xilinx Artix-7 FPGA
• Arty A7-35T board with Xilinx Artix-7 FPGA

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