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# RVCore Project, Arch Lab, Tokyo Tech

The RVCore Project is a research and development project
of the RISC-V soft processor highly optimized for FPGAs.

**RVCoreP** (**R**ISC-**V** **Core** **P**ipelined version) is one of the RISC-V soft processor cores of the RVCore Project.
It is an optimized RISC-V soft processor of five-stage pipelining.

{{:rvcorep.png?nolink&600|}}

**RVCoreP supports the following FPGA boards!**

- [[https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual|Nexys 4 DDR board]] with Xilinx Artix-7 FPGA
- [[https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual|Arty A7-35T board]] with Xilinx Artix-7 FPGA



## What's new

- 2020/06/25 : Released Ver.0.5.3 and support the Arty A7-35T FPGA board
- [[old2|2020/05/18]] : Add [[binary|the page]] how to build the RISC-V cross compiler and RISC-V binary files
- 2020/05/17 : Change of web page structure and release of Ver.0.5.1
- [[old1|2020/05/03]] : Added the setting method about New-line code
- 2020/03/04 : This page is released about Ver.0.4.6 !



## About RVCoreP

The main specifications of RVCoreP are shown below:

- An optimized RISC-V soft processor
- Adopt **RV32I** of RISC-V as an instruction set architecture, which is the basic 32-bit integer instruction set
- Adopt **five-stage pipelining**
  - Instruction fetch (If)
  - Instruction decode (Id)
  - Instruction execution (Ex)
  - Memory access (Ma)
  - Write back (Wb)
- Apply **three effective optimization methods** to improve the operating frequency
  - Instruction fetch unit optimization including the pipelined branch prediction mechanism
  - ALU optimization
  - Data alignment and sign-extension optimization for data memory output
- Implemented in **Verilog HDL**
- Run RISC-V programs compiled with RV32I
  - By Verilog HDL simulation using Verilator or Icarus Verilog
  - On the FPGA boards including **Xilinx Artix-7 FPGA**