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# RVCore Project, Arch Lab, Tokyo Tech The RVCore Project is a research and development project of the RISC-V soft processor highly optimized for FPGAs. **RVCoreP** (**R**ISC-**V** **Core** **P**ipelined version) is one of the RISC-V soft processor cores of the RVCore Project. It is an optimized RISC-V soft processor of five-stage pipelining. {{:rvcorep.png?nolink&600|}} **RVCoreP supports the following FPGA boards!** - [[https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual|Nexys 4 DDR board]] with Xilinx Artix-7 FPGA - [[https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual|Arty A7-35T board]] with Xilinx Artix-7 FPGA
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· Last modified: 2024/09/22 17:22 by
kise
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