RVCore Project

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# How to build the RISC-V cross compiler and RISC-V binary files that works with RVCoreP

## What's new

- 2020/05/18 : This page is released !

## Download source file

- The source code of the test benchmark of RVCoreP (2020/05/18): {{ :test.zip |test.zip}}

## Recommended environment

- Ubuntu 18.04 LTS

## Targeting RISC-V architecture

RV32I supporting a generic ELF/Newlib toolchain

- RV32I : 32bit basic integer instruction set
- (M extension, which is integer multiplication and division instructions, is software execution)

Target RISC-V ABI is ilp32 (32bit soft float)

## How to build RISC-V cross compiler

The following web page was used as a reference:\\
https://github.com/riscv/riscv-gnu-toolchain

--> Click here for details #

(1) Prerequisites

Several standard packages are needed to build the toolchain on Ubuntu.

```
$ sudo apt install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
```

(2) Getting the sources

Download the source files from GitHub

Use the version, "v20180629: June 29th, 2018 Toolchain Release"

```
$ git clone https://github.com/riscv/riscv-gnu-toolchain
$ cd riscv-gnu-toolchain
$ git checkout cb6b34b8581bfc72197aa24bd4f367d54db81b51
$ git submodule update --init --recursive
```

(3) Installation

To build the Linux cross-compiler, pick an install path.

If you choose the path `/opt/riscv`,
then add `/opt/riscv/bin` to your `PATH` now.

Then, run the following command:

```
$ ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32
$ sudo make
```

(4) Check the PATH

You will see output like this when you run the following command:

```
$ which riscv32-unknown-elf-gcc
/opt/riscv/bin/riscv32-unknown-elf-gcc

$ riscv32-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=...
COLLECT_LTO_WRAPPER=...
Target: riscv32-unknown-elf
Configured with: ...
Thread model: single
gcc version 8.1.0 (GCC)
```

<--

## How to build RISC-V binary files that works with RVCoreP

We explain build method using `test.zip` which is the source code of the test benchmark of RVCoreP.

--> Click here for details #

(1) Download the source code

```
$ wget http://www.arch.cs.titech.ac.jp/wk/rvcore/lib/exe/fetch.php?media=test.zip -O test.zip
```

(2) Extract the downloaded zip file

```
$ unzip test.zip
$ cd test
```

(3) Specify the installation directory of RISC-V cross compiler

You change `RISCV_PREFIX` in `Makefile` to proper path.

By default, `/opt/riscv/bin/riscv32-unknown-elf-` is set.

(4) Build the test benchmark

Execute the following command

```
$ make
make bin
cp main.bin _main.bin
dd if=/dev/zero bs=4k count=1 >> _main.bin
dd if=_main.bin bs=4k count=1 > main.bin
rm -f _main.bin
make hex4
make dump
make file
```

The following files are generated:

- `test.bin`  : the binary file
- `test.mem`  : the memory initialization file
- `test.dump` : the dump file

<--

## Description of each source file

The following describes the points required for each file.

--> Click here for details #

(1) Makefile

This Makefile does the following when the `make` command is executed

- Build the binary using the RISC-V cross compiler (make bin)
- Adjust the binary size
- Generate the memory initialization file (make hex4)
- Generate the dump file (make dump)
- Change the file names (make file)

Please see this file for details.

(2) main.lds

The linker script file

- set "riscv" as OUTPUT_ARCH
- The start address of the program executed by RVCoreP must be 0x00000000.
- specify the placement of each section
- The startup section is defined in startup.S

(3) startup.S

The startup routine program

- Initialize 32 integer registers and set stack pointer to 4KB (0x1000)
- The first instruction must be nop instruction.
- Jump to the main function

(4) simrv.c, simrv.h

The our system call source and header files

For the input and output of RVCoreP,
the same method for SimRV, a RISC-V processor simulator is used.

The input/output functions using HTIF tohost register are defined in these two files.

The HTIF tohost address is 0x40008000 in simrv.c.

```
volatile int *TOHOST_ADDR = (int *)0x40008000;
```

The control numbers of tohost function are defined in simrv.h.

```
#define CMD_PRINT_CHAR 1
#define CMD_POWER_OFF  2
```

(a) Print 8bit character data (CMD\_PRINT\_CHAR)

tohost [0000000000000001][00000000XXXXXXXX]

`XXXXXXXX` is the 8bit char data.

(b) Power off command (CMD\_POWER\_OFF)

tohost [0000000000000010][XXXXXXXXXXXXXXXX]

`XXXXXXXXXXXXXXXX` is the arbitrary data.

The four defined input/output functions are as follows.

- void simrv\_exit () : function exit
- void simrv\_putc (char c) : output 8bit character data
- void simrv\_puts (char *str) : output string data
- void simrv\_puth (unsigned int n) : output hex number data

(5) main.c, acker.c, fib.c, nqueen.c, qsort.c, main.h

The source code files of test benchmark program

The program output the characters using tohost

(6) test.bin, test.mem, test.dump

The output file

<--

## Contact

[[http://www.arch.cs.titech.ac.jp/|Kise Laboratory]], Department of Computer Science, School of Computing, [[https://www.titech.ac.jp/english/|Tokyo Institute of Technology]] (Tokyo Tech)

E-mail: miyazaki (at) arch.cs.titech.ac.jp

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