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start [2025/10/11 16:23] – [What's new] 104.233.166.1start [2025/10/11 16:23] (current) – [Verilog HDL simulation using Verilator] 104.233.166.1
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 It is an optimized RISC-V soft processor of five-stage pipelining. It is an optimized RISC-V soft processor of five-stage pipelining.
  
-{{:rvcorep.png?nolink&600|}}+{{:rvcorep.png?nolink&600|}}
  
 **RVCoreP supports the following FPGA boards!** **RVCoreP supports the following FPGA boards!**
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-## What's new+## What's new
  
 - 2020/06/25 : Released Ver.0.5.3 and support the Arty A7-35T FPGA board - 2020/06/25 : Released Ver.0.5.3 and support the Arty A7-35T FPGA board
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 ``` ```
-$ vivado main.xpr &+$ vivado main.xpr &
 ``` ```
  
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 Execute the following process according to the used set of logic synthesis and placement and routing. Execute the following process according to the used set of logic synthesis and placement and routing.
  
-- Right click on synth_* for logic synthesis and select "Make Active" +- Right click on synth_* for logic synthesis and select "Make Active" 
-- Click "Generate Bitstream" in Vivado project manager+- Click "Generate Bitstream" in Vivado project manager
  
 By default, the operating frequency of the processor is set to 160MHz. By default, the operating frequency of the processor is set to 160MHz.
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 (3) Write the generated bitstream to the FPGA board (3) Write the generated bitstream to the FPGA board
  
-- Click "Open Hardware Manager" in Vivado project manager to open the hardware manager+- Click "Open Hardware Manager" in Vivado project manager to open the hardware manager
  
-- Click "Open target" and "Auto Connect" to recognize the FPGA board+- Click "Open target" and "Auto Connect" to recognize the FPGA board
  
-- Click "Program device" and specify Bitstream file+- Click "Program device" and specify Bitstream file
  
-- Click "Program" to write bitstream to FPGA board+- Click "Program" to write bitstream to FPGA board
  
 When the bitstream data is correctly written to the Nexys 4 DDR board, When the bitstream data is correctly written to the Nexys 4 DDR board,
-the DONE LED lights up and "00000000" is displayed on the 8-digit 7-segment LEDs.+the DONE LED lights up and "00000000" is displayed on the 8-digit 7-segment LEDs.
  
 (4) Prepare for 8M baud serial communication (4) Prepare for 8M baud serial communication
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 ``` ```
-$ python3 serial_rvcorep.py 8 "test.bin"+$ python3 serial_rvcorep.py 8 "test.bin"
 ``` ```
  
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 If you execute the test benchmark `test/test.bin`, the output to the 7-segment LEDs is `000000A0`. If you execute the test benchmark `test/test.bin`, the output to the 7-segment LEDs is `000000A0`.
  
-When using Nexys 4 DDR board and the button "BTNU" is pressed, the 7-segment LED shows the number of execution cycles.+When using Nexys 4 DDR board and the button "BTNU" is pressed, the 7-segment LED shows the number of execution cycles.
 If you execute the test benchmark `test/test.bin`, the output　to the 7-segment LEDs is `000088D6`. If you execute the test benchmark `test/test.bin`, the output　to the 7-segment LEDs is `000088D6`.
  
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start.1760167396.txt.gz · Last modified: 2025/10/11 16:23 by 104.233.166.1