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start [2024/09/22 17:34] – [Getting started guide] kise | start [2024/12/09 00:40] (current) – [Implementation and execution on a FPGA board] 94.103.125.62 | ||
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``` | ``` | ||
- | $ vivado main.xpr & | + | $ vivado main.xpr & |
``` | ``` | ||
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Execute the following process according to the used set of logic synthesis and placement and routing. | Execute the following process according to the used set of logic synthesis and placement and routing. | ||
- | - Right click on synth_* for logic synthesis and select | + | - Right click on synth_* for logic synthesis and select |
- | - Click "Generate Bitstream" | + | - Click "Generate Bitstream& |
By default, the operating frequency of the processor is set to 160MHz. | By default, the operating frequency of the processor is set to 160MHz. | ||
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(3) Write the generated bitstream to the FPGA board | (3) Write the generated bitstream to the FPGA board | ||
- | - Click "Open Hardware Manager" | + | - Click "Open Hardware Manager& |
- | - Click "Open target" | + | - Click "Open target& |
- | - Click "Program device" | + | - Click "Program device& |
- | - Click "Program" | + | - Click "Program& |
When the bitstream data is correctly written to the Nexys 4 DDR board, | When the bitstream data is correctly written to the Nexys 4 DDR board, | ||
- | the DONE LED lights up and "00000000" | + | the DONE LED lights up and "00000000& |
(4) Prepare for 8M baud serial communication | (4) Prepare for 8M baud serial communication | ||
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``` | ``` | ||
- | $ python3 serial_rvcorep.py 8 "test.bin" | + | $ python3 serial_rvcorep.py 8 "test.bin" |
``` | ``` | ||
start.1726994096.txt.gz · Last modified: 2024/09/22 17:34 by kise · Currently locked by: 104.249.31.95