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start [2024/09/22 17:28] – kisestart [2024/12/09 00:40] (current) – [Implementation and execution on a FPGA board] 94.103.125.62
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   - By Verilog HDL simulation using Verilator or Icarus Verilog   - By Verilog HDL simulation using Verilator or Icarus Verilog
   - On the FPGA boards including **Xilinx Artix-7 FPGA**   - On the FPGA boards including **Xilinx Artix-7 FPGA**
- 
- 
- 
  
 ## Download source file ## Download source file
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 This source code is released under the MIT License, see LICENSE.txt. This source code is released under the MIT License, see LICENSE.txt.
  
---> Change log #^+### Change log
  
 - Ver.0.5.3 : The version that supports Arty A7-35T FPGA board - Ver.0.5.3 : The version that supports Arty A7-35T FPGA board
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 - Ver.0.4.6 : The version used in our submitted manuscript - Ver.0.4.6 : The version used in our submitted manuscript
  
-<-- 
  
  
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 - [[https://pythonhosted.org/pyserial/|pySerial]] for serial communication with FPGA board - [[https://pythonhosted.org/pyserial/|pySerial]] for serial communication with FPGA board
  
---> Install command #+### Install command
  
 Install verilator by the following command. Install verilator by the following command.
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 $ pip3 install pyserial $ pip3 install pyserial
 ``` ```
- 
-<-- 
  
  
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 ``` ```
  
---> Verilog HDL simulation using Verilator #+### Verilog HDL simulation using Verilator
  
 You execute the following commands on the recommended environment. You execute the following commands on the recommended environment.
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 The memory file of the test benchmark is `test/test.mem`. The memory file of the test benchmark is `test/test.mem`.
  
---> Execution result when running `test/test.mem` #+### Execution result when running `test/test.mem`
  
 ``` ```
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 The information such as IPC (Instructions Per Cycle) and branch prediction hit rate is output to the console after running simulation. The information such as IPC (Instructions Per Cycle) and branch prediction hit rate is output to the console after running simulation.
  
-<--+
  
 (3) Execute the Dhrystone and Coremark benchmarks by the Verilog HDL simulation (3) Execute the Dhrystone and Coremark benchmarks by the Verilog HDL simulation
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 The execution results of dhrystone3, coremark3, and 19 benchmarks of Embench are summarized in the file `result.txt`. The execution results of dhrystone3, coremark3, and 19 benchmarks of Embench are summarized in the file `result.txt`.
  
-<-- 
  
---> Implementation and execution on a FPGA board #+### Implementation and execution on a FPGA board
  
 You execute the following process in the directory of the downloaded source code on the recommended environment. You execute the following process in the directory of the downloaded source code on the recommended environment.
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 ``` ```
-$ vivado main.xpr &+$ vivado main.xpr &amp;
 ``` ```
  
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 Execute the following process according to the used set of logic synthesis and placement and routing. Execute the following process according to the used set of logic synthesis and placement and routing.
  
-- Right click on synth_* for logic synthesis and select "Make Active" +- Right click on synth_* for logic synthesis and select &quot;Make Active&quot; 
-- Click "Generate Bitstream" in Vivado project manager+- Click &quot;Generate Bitstream&quot; in Vivado project manager
  
 By default, the operating frequency of the processor is set to 160MHz. By default, the operating frequency of the processor is set to 160MHz.
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 (3) Write the generated bitstream to the FPGA board (3) Write the generated bitstream to the FPGA board
  
-- Click "Open Hardware Manager" in Vivado project manager to open the hardware manager+- Click &quot;Open Hardware Manager&quot; in Vivado project manager to open the hardware manager
  
-- Click "Open target" and "Auto Connect" to recognize the FPGA board+- Click &quot;Open target&quot; and &quot;Auto Connect&quot; to recognize the FPGA board
  
-- Click "Program device" and specify Bitstream file+- Click &quot;Program device&quot; and specify Bitstream file
  
-- Click "Program" to write bitstream to FPGA board+- Click &quot;Program&quot; to write bitstream to FPGA board
  
 When the bitstream data is correctly written to the Nexys 4 DDR board, When the bitstream data is correctly written to the Nexys 4 DDR board,
-the DONE LED lights up and "00000000" is displayed on the 8-digit 7-segment LEDs.+the DONE LED lights up and &quot;00000000&quot; is displayed on the 8-digit 7-segment LEDs.
  
 (4) Prepare for 8M baud serial communication (4) Prepare for 8M baud serial communication
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 ``` ```
-$ python3 serial_rvcorep.py 8 "test.bin"+$ python3 serial_rvcorep.py 8 &quot;test.bin&quot;
 ``` ```
  
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 The following execution result is output via serial communication. The following execution result is output via serial communication.
  
---> Execution result when running `test.bin` #+### Execution result when running `test.bin`
  
 ``` ```
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 If you execute the test benchmark `test/test.bin`, the output　to the 7-segment LEDs is `000088D6`. If you execute the test benchmark `test/test.bin`, the output　to the 7-segment LEDs is `000088D6`.
  
-<-- 
  
 This program is terminated by Ctrl-C. This program is terminated by Ctrl-C.
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 If you want to send the binary file of the program to the FPGA board again and execute it, proceed from step (3). If you want to send the binary file of the program to the FPGA board again and execute it, proceed from step (3).
  
-<-- 
  
  
start.1726993685.txt.gz · Last modified: 2024/09/22 17:28 by kise · Currently locked by: 64.95.10.106