Time Table
09:00-09:25 Opening Session 09:25-10:15 Processor Architecture 10:30-11:45 Invited Talk 13:00-14:15 Accelerator 14:30-15:20 Parallel Software & Tools
Program
Opening Session (09:00-09:25)
Processor Architecture (09:25-10:15)
chair: Takefumi MIYOSHI
The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors
Yosuke Mori, Kenji Kise (Tokyo Institute of Technology - Tokyo, Japan)
Improvement of Execution Efficiency on the MX Core
Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto University - Kumamoto, Japan)
Invited Talk(10:30-11:45)
chair: Hironori Nakajo
Parallel Implementation of Multiple-Precision Arithmetic and 2.576 Trillion Digits of Pi Calculation on a Massively Parallel Cluster of Multi-Core Processors
Prof. Daisuke Takahashi, Ph.D. (University of Tsukuba - Tsukuba, Japan)
In this talk, we present efficient parallel algorithms for multiple-precision arithmetic operations on a massively parallel cluster of multi-core processors. In multiple-precision multiplication of more than several thousand decimal digits, FFT-based multiplication is the fastest method. We will first present parallel FFT algorithms on a massively parallel cluster of multi-core processors. Then we will review the parallelization of multiple-precision arithmetic. The last part of the talk will present the outline of more than 2.576 trillion decimal digits of pi calculation.
Accelerating Systems (13:00-14:15)
chair: Tsutomu Yoshinaga
Accurate Measurements and Precise Modeling of Power Dissipation of CUDA Kernels toward Power Optimized High Performance CPU-GPU Computing
Reiji Suda, DaQi Ren (The University of Tokyo & JST, CREST - Tokyo, Japan)
CheCUDA: A Checkpoint/Restart Tool for CUDA Applications
Hiroyuki Takizawa, Katsuto Sato, Kazuhiko Komatsu, Hiroaki Kobayashi (Tohoku University - Sendai, Japan)
SMP Based Solver for Large Binary Systems
Nikhil Jain, Brajesh Pande, Phalguni Gupta (Indian Institute of Technology Kanpur - Kanpur, India)
Parallel Software & Tools (14:30-15:20)
chair: Shoichi Hirasawa
A Study of an Infrastructure for Research and Development of Many-Core Processors
Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise (Tokyo Institute of Technology - Tokyo, Japan)
Key Elements Tracing Method for Parallel XML Parsing in Multi-Core System
Xiaosong Li, Hao Wang, Taoying Liu, Wei Li (Chinese Academy of Science, Beijing, China)