ScalableCore System

A Scalable Many-core Processor Simulator by Employing over 100 FPGAs

 
 

This page is about ScalableCore system, an FPGA-based cycle-accurate many-core processor simulator.

 

Download

  1. •ScalableCore System 3.4 (Verilog HDL Source Code)


Document

  1. •Ping-Pong on Multiple FPGAs


Conference Paper

  1. •ARC 2012 [Paper] [Slide]

  2. •HEART 2012 [Paper] [Slide]


Fast and Cycle-Accurate Many-core Processor Simulator