International Workshop on Advanced Low Power Systems
held in conjunction with
20th International Conference on Supercomputing
July 1, 2006
Cairns, Australia


eGentlenessf is an important keyword in the both current and future technologies in all over the world. Gentle to human being, gentle to our surroundings, gentle to the earth, and so on. Low-power technology is believed to be one of the most indispensable technologies for the gentleness.

ALPS focuses on the current technological challenges in developing power-aware computing systems, ranging from servers to portable and embedded devices. The goal of this workshop is to bring all aspects of power-aware computing from industry and academia. The topics of the workshop include any issue related to power-aware computing, including fields as follows.

* Microarchitecture design
* Logic and digital circuit design
* Embedded system design
* Power-aware HPC architecture
* Power-aware compiler and operating system design
* Power-aware middleware
* Power-aware run-time systems
* Circuit/architecture/OS cooperation
* Power-aware applications and algorithms
* Tools for power-aware hardware-software design and analysis
* Power-aware fault tolerant systems
* Thermal management

8 papers are selected for the workshop based on refereed full papers by the program committee after careful consideration. All papers here are going to create the way to the new aspects of low power systems.

We thank all the participants and the program committee for successful start of the workshop ALPS.

The support of the committee of International Conference of Supercomputing (ICS06) is also gratefully acknowledged.


General Chair:
Hironori Nakajo,
Tokyo University of Agriculture and Technology, Japan

Program Chair:
Toshinori Sato,
Kyushu University, Japan

Publicity Chair:
Kenji Kise, Tokyo Institute of
Technology, Japan

Program Committee:
Toshinori Sato, Kyushu University, Japan
David Albonesi, Cornell University, USA
Pradip Bose, IBM T. J. Watson Research Center, USA
David Brooks, Harvard University, USA
Naehyuck Chang, Seoul National University, Korea
Pai Chou, University of California, Irvine, USA
Nikil Dutt, University of California, Irvine, USA
Farzan Fallah, Fujitsu Labs of America, USA
Pierfrancesco Foglia, University of Pisa, Italy
Masahiro Goshima, University of Tokyo, Japan
José González, Intel Barcelona Research Center, Spain
Kenji Kise, Tokyo Institute of Technology, Japan
Tadahiro Kuroda, Keio University, Japan
José F. Martínez, Cornell University, USA
Vasily Moshnyaga, Fukuoka University, Japan
Hiroshi Nakashima, Toyohashi University of Technology, Japan
Vijaykrishnan Narayanan, Pennsylvania State University, USA
Sri Parameswaran, University of New South Wales, Australia
Mitsuhisa Sato, University of Tsukuba, Japan
Youngsoo Shin, KAIST, Korea
Hiroyuki Tomiyama, Nagoya University, Japan

08:30-09:15 Session 1: Invited Talk, Chair: Hironori Nakajo

Ø        Energy-Efficient Embedded System Design at 90nm and Below-- A System-Level Perspective --
Tohru Ishihara (
Kyushu University, Japan)


09:30-11:10 Session 2: Power-aware Compilation, Chair: Kenji Kise

Ø        Dynamic Voltage and Frequency Scaling Method based on Statistical Analysis
H. Sasaki, Y. Ikeda, M. Kondo, and H. Nakamura (University of Tokyo, Japan)

Ø        Empirical Study for Optimization of Power-Performance with On-Chip Memory
C. Takahashi, M. Sato, D. Takahashi, T. Boku, H. Nakamura, M. Kondo,and M. Fujita (University of Tsukuba, Japan)

Ø        Performance Evaluation of Compiler Controlled Power Saving Scheme
J. Shirako, M. Yoshida, N. Oshiyama, Y. Wada, H. Nakano, H. Shikano, K. Kimura, H. Kasahara (Waseda University, Japan)

Ø        Optimizing the Profile-Guided Real-Time Voltage Scheduling Considering the System Maximum Frequency
H. Yi, X. Yang, and J. Chen (National University of Defense Technology, P.R.China)

11:25-12:45 Session 3: Low-power Design, Chair: Toshinori Sato

Ø        Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption
J. Yao, H. Shimada, S. Tomita, Y. Nakashima, S. Mori (Kyoto University, Japan)

Ø        Reducing Energy in Instruction Caches by Using Multiple Line Buffers with Prediction
K. Ali, M. Aboelaze, and S. Datta (York University, Canada)

Ø        Power and Performance Advantages of the Highly Clustered Microarchitecture
Y. Sato, K. Suzuki, and T. Nakamura (Tohoku University, Japan)

Ø        Low Power FSM Synthesis with Testability
S. Chaudhury, J. S. Rao, and S. Chattopadhyay (Indian Institute of Technology Khargpur, India)