SimCore is a project name to provide computer architecture core tools including processor simulators.
We are developing a SimCore/Alpha RealScalar Simulator
for research and education activities.
Its design policy is to keep the source code readable (enjoyable and easy
to read ) and simple.
SimCore/Alpha RealScalar is a cycle-accurate performance simulator modeling
a 5 stages pipelined scalar processor.
It has simple instruction cache, data cache and branch predictor.
SimAlpha old versions are downloadable from SimAlpha Homepage.
(1) Download a package file SimCore-RealScalar-0.9.30.tgz from this site.
(2) Unpack the file with a command "tar xvfz SimCore-RealScalar-0.9.30.tgz".
(3) Change directory and make "cd ReaScalar-0.9.30; make". SimCore_RealScalar is made.
(4) Download a sample image file dhry-050k.txt from this site. This is a 50000 loop dhrystone.
(5) Start the simulation with a command "SimCore_RealScalar dhry-050k.txt".
(6) See README.txt in the directorey RealScalar-0.9.30 for details.
If you have trouble, Please send an E-mail to kis@is.uec.ac.jp .
2004-05-24: SimCore/Alpha RealScalar Version 1.0r1 is available.
2003-10-03: SimCore/Alpha RealScalar Version 0.9.30 is available.
This is a test version.
SimCore/Alpha RealScalarr Version 0.9.30 Plathomes
Source Code (in text format)
This page is written by Kenji KISE. kis@is.uec.ac.jp