International Workshop on Advanced Low Power Systems
http://www.arch.cs.titech.ac.jp/ALPS/
held in conjunction with
21st International Conference on Supercomputing
Preface
‘Thoughtfulness’ is an important keyword in the both current and future technologies in all over the world. Thoughtful to human being, thoughtful to our surroundings, thoughtful to the earth, and so on. Low-power technology is believed to be one of the most indispensable technologies for the thoughtfulness.
ALPS focuses on the current technological challenges in developing power-aware computing systems, ranging from servers to portable and embedded devices. The goal of this workshop is to bring all aspects of power-aware computing from industry and academia. The topics of the workshop include any issue related to power-aware computing, including fields as follows.
* Microarchitecture
design
* Logic and digital circuit design
* Embedded system design
* Power-aware HPC architecture
* Power-aware compiler and operating system design
* Power-aware middleware
* Power-aware run-time systems
* Circuit/architecture/OS cooperation
* Power-aware applications and algorithms
* Tools for power-aware hardware-software design and analysis
* Power-aware fault tolerant systems
* Thermal management
Ø
An Under 2W 100GOPS Video Recognition Processor Based on a Linear Array of 128 4-Way VLIW Processing Elements.
Shorin Kyo (NEC Corporation)
Ø
Optimal Pipeline Depth with Pipeline Stage Unification Adoption.
Jun Yao, Hajime Shimada, Shinobu Miwa, and Shinji Tomita (Kyoto University)
Ø
VCLEARIT: A VLSI CMOS Circuit Leakage Reduction Technique For Nanoscale Technologies.
Preetham Lakshmikanthan and Adrian Nunez (Syracuse University)
Ø
Leakage Energy Reduction in Cache Memory by Data Compression.
Kiyofumi Tanaka and Takahiro Kawahara (Japan Advanced Institute of Science and Technology)
Ø Preventing Timing Errors on Register Writes: Mechanisms of Detections and Recoveries.
Hidetsugu Irie (Japan Science and Technology Agency), Ken Sugimoto, Masahiro Goshima, and Suichi Sakai (The University of Tokyo)
Ø Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation.
Mihaela Malita (St. Anselm College), Gheorghe Stefany (BrightScale Inc.), and Dominique Thiebaut (Smith College)
Ø Fine-grain Compensation Method with Consideration of Trade-offs between Computation and Data Transfer for Power Consumption.
Takefumi Miyoshi and Nobuhiko Sugino (Tokyo Institute of Technology)
Submission of Papers
People who would like to participate in this event are invited to submit
a paper (or an extended abstract) to the workshop general chair via email
(ALPS07@arch.cs.titech.ac.jp). Submitted papers should follow the IEEE
conference format and must not exceed 8 pages in length. Papers must be
in submitted in PDF format. Papers that are excessively long may be rejected
without review. All accepted papers will be made available at the workshop.
Important dates:
Papers due : May 10, 2007 (deadline extended by one week)
Acceptance notices: May 25, 2007
Workshop date : June 17 (half day), 2007
General Chair:
Hironori Nakajo,
Publication Chair:
Toshinori
Program Chair:
Kenji Kise, Tokyo Institute of Technology, Japan
Program Committee:
Pradip Bose, IBM T. J. Watson Research Center, USA
David Brooks, Harvard University, USA
Naehyuck Chang, Seoul National University, Korea
Nikil Dutt, University of California, Irvine, USA
Farzan Fallah, Fujitsu Labs of America, USA
Pierfrancesco Foglia, University of Pisa, Italy
Masahiro Goshima, University of Tokyo, Japan
Tohru Ishihara, Kyushu University, Japan
Vasily Moshnyaga, Fukuoka University, Japan
Hiroshi Nakashima, Kyoto University, Japan
Vijaykrishnan Narayanan, Pennsylvania State University, USA
Sri Parameswaran, University of New South Wales, Australia
Mitsuhisa Sato, University of Tsukuba, Japan
Youngsoo Shin, KAIST, Korea
Hiroyuki Tomiyama, Nagoya University, Japan